State memory elements are conventionally referred to as registers, latches or column latches and are used for an efficient driving of nonvolatile memories such as EEPROMs or flash memories. A nonvolatile memory can retain its data even if the supply voltage has been turned off. In comparison to volatile memories, also referred to as RAMs, the programming or writing of EEPROM or flash memories is relatively slow. The so called hot carrier charge injection method or the Fowler-Nordheim tunneling mechanism is typically used for programming EEPROMs or flash memories. The column latch described below is designed for use together with EEPROM or flash memories that are programmed and erased with the Fowler-Nordheim tunneling mechanism. To operate such a memory efficiently, it is subdivided into areas several bytes wide, so-called pages. The memory cells of a page are accessible via the latch with only one write or read operation. The latches are implemented with high-voltage transistors.
The circuit arrangement proceeds from a circuit in which a latch is connected via a switch to a bit line of a nonvolatile memory cell. To program the memory cell, a corresponding value is first written into the latch. This writing to the latch takes place with low supply voltages. However, since the starting or threshold voltage of the high-voltage transistors in the latch is higher than that for low-voltage transistors, and the on-state resistance of the aforementioned switch increases sharply for a low supply voltage, for example, into the range of several 100 kiloohms, it is problematic to reliably store a value in the latch. Due to the high on-state resistance at low supply voltages, even small currents that cause a voltage drop at the on-state resistance are sufficient to prevent the voltage from reliably exceeding or falling below the switching point of the latch. This property intensifies at low temperatures, whereby the threshold voltage of the high-voltage transistors, and thus the on-state resistance of the switch, increase further. To reduce the on-state resistance, the geometry of the switch would have to be enlarged to such an extent that the latch could no longer be constructed in a spatially efficient manner and would additionally represent a very high capacitive load for a data driver connected to it.